Electronic Design Laboratory
received the M.S. and Ph.D. degrees in electronic engineering, from the University of Genova (Italy), in 1996 and 2001 respectively. During his Ph.D. he worked on analog microelectronic supervised learning systems with emphasis in silicon implementation of neural networks.
In the 2001 he joined Accent S.p.A., a joint venture between ST Microelectronics and Cadence Design System, as Senior Consulting Engineer. Here he worked for eight years as ASIC designer for several digital designs in different fields of applications such as automotive, fingerprint sensors and multimedia.
In 2009 he moved to the Istituto Italiano di Tecnologia (IIT) in Genoa joining to the TeleRobotics and Applications (TERA) Department. In 2011 he moved to the Robotic, Brain and Cognitive Sciences (RBCS) Department of IIT.
He is currently interested in low power computing systems for mobile robots and humanoids including FPGAs design, stereo vision and low power parallel architectures. He is also author of some international conference papers and patents.
- Title: Disposizione circuitale multiprocessore per l'esecuzione di un algoritmo di visione stereoscopica e sistema di visione stereoscopica ed elusione di ostacoli per robot mobili
Inventors:Francesco Diotalevi, Amir Fijany, Jean-Guy Fontaine, Michael Montvelishsky.
Assignee:Fondazione Istituto Italiano di Tecnologia
Priority date: February 28, 2011
- Title: Metodo per stimare un modello su architetture MIMD multi-core e many-core
Inventors:Francesco Diotalevi, Amir Fijany, Giulio Sandini
Assignee:Fondazione Istituto Italiano di Tecnologia
Priority date:March 2, 2012
- F. Diotalevi, A. Fijany and G. Sandini, "Wavefront/Systolic Algorithms for Implementation of Stereo Vision and Obstacle Avoidance Computations on a Very Low Power MIMD Many-Core Parallel Architecture: Applications for Mobile Systems and Wearable Visual Guidance", Chapter 10 of book "Current Advancements in Stereo Vision", pp. 199-224, ISBN: 978-953-51-0660-9, Published: July 11, 2012.
- F. Boi, T. Moraitis, V. De Feo, F. Diotalevi, C. Bartolozzi, G. Indiveri and A. Vato, A Bidirectional Brain-Machine Interface Featuring a Neuromorphic Hardware Decoder, Frontiers in Neuroscience, vol 10, pp.: 563, ISSN: 1662-453X, 09 December 1016.
- M. Crepaldi, G.N. Angotzi, A. Maviglia, F. Diotalevi, and L. Berdondini, "A 5 pJ/pulse at 1-Gpps Pulsed Transmitter Based on Asynchronous Logic Master-Slave PLL Synthesis", IEEE Transaction on CIRCUITS AND SYSTEMS, vol.65, no.3, March 2018, pp 1096-1109, ISSN 1549-8328.
- M. Valle, F. Diotalevi, A Dedicated Very Low Power Analog VLSI Architecture for Smart Adaptive Systems, Special Issue on Hardware Implementations of Soft Computing Techniques, Applied Soft Computing, Elsevier Science Publisher, No 4, 2004, pp. 206 - 226, (ISSN: 1568-4946).
International conference proceedings
D. Baratta, D.D. Caviglia, F. Diotalevi, M. Valle, R. Parenti, Leap-frog: a Programmable VLSI Neural Processor Architecture for Real-Time MLP-based Neural Networks Implementation, in Proc. of the 6th International Conference on Microelectronics for Neural Networks, Evolutionary & Fuzzy Systems MicroNeuro’97, printed in Dresden, Germany, Dresden (Germany), Sept. 24 - 26, 1997, pp. 25 - 30 (ISBN: 3 – 86005 – 190 – 3).
D. Baratta, G. M. Bo, D. D. Caviglia, F. Diotalevi, and M. Valle, Microelectronic Implementation of Artificial Neural Networks, in Proc. of the 5th Electronic Devices and Systems Conference 1998 EDS'98, published by the Technical University of Brno, printed in Brno, June 11 - 12 1998, Brno, Czech Republic, pp. VI – IX (ISBN: 80 – 214 – 1198 – 8).
D. Baratta, F. Diotalevi, M. Valle and D. D. Caviglia, Gradient Descent Learning Algorithms for Hierarchical Neural Networks: A Case Study in Industrial Quality Control, in Proc. of the International Conference on Artificial and Natural Neural Networks IWANN’99, Springer – Verlag, printed in Germany, Alicante, Spain, 2 – 4 June 1999, Vol. II pp 578 – 587 (ISBN: 3 – 540 – 66068 – 2).
F. Diotalevi, G.M. Bo, D.D. Caviglia, and M. Valle, Evaluation and Validation of Local and Adaptive Weight Perturbation Learning Algorithms for Optical Character Recognition Applications, in Proc. of the Third International ICSC Symposia on Intelligent Industrial Automation (IIA'99) and Soft Computing (SOCO'99), ICSC Academic Press, Canada/Switzerland, Genova, 1-4 June, 1999, pp. 508 - 512 (ISBN: 3 - 906454 - 17 – 7).
F. Diotalevi, M. Valle, G.M. Bo, E. Biglieri, and D.D. Caviglia, Analog CMOS Current Mode Neural Primitives, ISCAS'2000, IEEE International Symposium on Circuits and Systems, IEEE Press, Piscataway, NJ, Geneva, Switzerland, 28 – 31 May, 2000, pp. I 419 – I 422 (ISBN: 0 – 7803 – 5485 – 0).
F. Diotalevi, M. Valle, G.M. Bo, E. Biglieri, and D.D. Caviglia, An Analog On-Chip Learning Circuit Architecture of the Weight Perturbation Algorithm, ISCAS'2000, IEEE International Symposium on Circuits and Systems, IEEE Press, Piscataway, NJ, Geneva, Switzerland, 28 – 31 May, 2000, pp. II 717 – II 720 (ISBN: 0 – 7803 – 5485 – 0).
F. Diotalevi, M. Valle, and D.D. Caviglia, Evaluation of Gradient Descent Learning Algorithms with An Adaptive Local Rate Technique for Hierarchical Feed Forward Architectures, IEEE-INNS-ENNS International Joint Conference on Neural Networks, IEEE Press, Piscataway, NJ, Como, Italy, 24 - 27 July, 2000 (ISBN: 0 – 7695 – 0619 – 4).
F. Diotalevi, M. Valle, G.M. Bo and D.D. Caviglia, A VLSI Architecture for Weight Perturbation On Chip Learning Implementation, IEEE-INNS-ENNS International Joint Conference on Neural Networks, IEEE Press, Piscataway, NJ, Como, Italy, 24 - 27 July, 2000 (ISBN: 0 – 7695 – 0619 – 4).
F. Diotalevi, M. Valle, Weight perturbation learning algorithm with local learning rate adaptation for the classification of remote-sensing images, 9th European Symposium on Artificial Neural Networks, ESANN’01, Bruges (Belgium), 25 – 27 April, 2001, pp. 217 - 222 (D-Facto Publisher, B 1140 Evere, Belgium, ISBN 2 – 930307-01-3).
F. Diotalevi, M. Valle, An analog CMOS four quadrant current-mode multiplier for low power artificial neural networks implementation, 15th European Conference on Circuit Theory and Design, ECCTD’01: "Circuit Paradigm in the 21st Century", Helsinki University of Technology, Espoo, Finland, 28 – 31 august 2001, pp. III – 325 – III 328 (ISBN: 951 – 22 – 5572 – 3).
F. Diotalevi, A. Fijany, M. Montvelishsky and J-G. Fontaine, “Very Low Power Parallel Implementation of Stereo Vision Algorithm on a Solar Cell Powered MIMD Many Core Architecture”, 2011 IEEE Aerospace Conference, March 5-12, 2011, Big Sky, Montana, pp. 1-13 (ISBN: 978-1-4244-7350-2).
S. Safari, A. Fijany, F. Diotalevi, F. Hosseini, "Highly parallel and fast implementation of stereo vision algorithms on MIMD many-core Tilera architecture", 2012 IEEE Aerospace Conference, March 3-10, 2012, Big Sky, Montana, pp. 1-11 (ISBN: 978-1-4577-0556-4).
A. Fijany, F.Diotalevi, “A cooperative search algorithm for highly parallel implementation of RANSAC for model estimation on Tilera MIMD architecture", 2012 IEEE Aerospace Conference, March 3-10, 2012, Big Sky, Montana, pp. 1-14 (ISBN: 978-1-4577-0556-4).
F. Boi, F. Diotalevi, F. Stefanini, G. Indiveri, C. Bartolozzi, A. Vato, "A modular configurable system for closed-loop bidirectional brain-machine interfaces", 7th Annual International IEEE EMBS Conference on Neural Engineering, Montpellier, France, 22 - 24 April, 2015.
Brayda L., Traverso F, Giuliani L., Diotalevi F., Repetto S., Sansalone S., Trucco A. and Sandini G., "Spatially selective binaural hearing aids". BodySenseUX Workshop on Full-Body and Multisensory Experience, ACM UBICOMP 2015 , Osaka, Japan, September 7-11, 2015.
Bartolozzi C., Motto Ros P. Diotalevi F., Jamali N., Natale L., Crepaldi M., Demarchi D., ”Event-driven encoding of off-the-shelf tactile sensors for compression and latency optimisation for robotic skin”, 2017 IEEE/RSJ International Conference on Intelligent Robots and Systems (IROS). September 24–28, 2017, Vancouver, BC, Canada
Crepaldi M., Angotzi G.N., Maviglia A., Diotalevi F.., Berdondini L., “A 5 pJ/pulse at 1-Gpps Pulsed Transmitter Based on Asynchronous Logic Master-Slave PLL Synthesis”, IEEE Transactions on Circuits and Systems, 31 Oct 2017, DOI: 10.1109/TCSI.2017.2762159.
A. Rossetta, F. Diotalevi, E. Slenders, G. Tortarolo, M. Castello, M. Buttafava, F. Villa, A. Tosi, M. Crepaldi, A. Diaspro and G. Vicidomini, “Time-Resolved Fluorescence Detection with Single-Photonavalanche-Diode Array - Applications in Life Sciences”, IVSLA International School on Nanoscale Optical Microscopy, 11-14 June 2019, Venice, Italy
Papers on Alta Frequenza (AEI review)
- F. Diotalevi, M. Valle, Analog CMOS Current Mode Primitives for Feed-Forward Neural Networks, Alta Frequenza, Rivista di Elettronica, edita da AEI, Vol. 12, No 1, Gennaio-Febbraio-Marzo 2001, pp. 63 – 67 (ISSN: 1120 – 1908).
- F. Diotalevi, M. Valle, Stochastic Learning Algorithms for the Classification of Remote-Sensing Images, Alta Frequenza, Rivista di Elettronica, edita da AEI, Vol. 13, No 5, Settembre - Ottobre 2001, pp. 60 – 64 (ISSN: 1120 – 1908).
National conference proceedings
- M. Valle, F. Diotalevi, G.M. Bo, E. Biglieri, and D.D. Caviglia, An Analog On-Chip Learning Architecture based on Weight Perturbation Algorithm and on Current Mode Translinear Circuits, in Proc. of the Eleventh Italian Workshop on Neural Nets (WIRN VIETRI-99), Vietri sul Mare (SA), 20 – 22 May 1999, Springer-Verlag, 1999, pp. 308 – 313 (ISBN: 1 – 85233 – 177 - 1).
- A. Rossetta, F. Diotalevi, E. Slenders, G. Tortarolo, M. Castello, M. Buttafava, F. Villa, M. Crepaldi, A. Diaspro and G. Vicidomini, Time-resolved Fluorescence Detection with Single-Photonavalanche-Diode Array Applications in Life Sciences, in IVSLA International School on Nanoscale Optical Microscopy, 11-14 June 2019, Venice, Italy.
Winner in "ICT and Social Innovation" with Glassesnse design, a smart wearable device helping people with hearing aids. November 4th 2016